Below are job opportunities available in Cavium offices in San Jose, CA, Marlborough, MA, and other east-coast locations. Please send your resume to USjobs@caviumnetworks.com. Resumes received without the appropriate job code in the subject line of emails will not be considered.

Cavium offers attractive salaries and benefits, cutting-edge technology, and a progressive work environment.  Our culture appreciates diversity, fosters personal growth, values teamwork, shares success, and rewards excellence.  We are an affirmative action/equal-opportunity employer and we seek to hire qualified applicants from diverse backgrounds.

Jobs in San Jose, CA

Verification Engineer
RTL Design Engineer
Sr. Validation Engineer
Digital Circuit Design Engineer
Design for test (DFt) Architect
Mixed Signal Circuit Design Engineer
Mixed Signal Mask Designer
Analog CAD Engineer

• Research and develop advanced receiver algorithms for WCDMA/HSPA+, LTE modem
• Simulate, analyze and optimize fixed-point designs in comprehensive PHY Simulator under various RF imperfections and fading channels to meet modem performance requirements.
• Work with HW and SW design teams to implement and verify the feature on real-time multi-core SoC.
• Guide System Test to characterize and optimize modem performance in lab and on the field.

• MS in Electrical Engineering with a minimum of 6years of related experience or PhD in Electrical Engineering with a minimum of 3years of related experience.
• Prior experience in developing signal processing algorithms for WCDMA/HSPA+ is a must.Experience with LTE PHY algorithms development is a plus.
• Strong theoretical background in Wireless Communications and Digital Signal Processing.
• Strong expertise in designing mobile receiver algorithms: RAKE,Multi-user Detection, IRC, Interference Cancellation, MIMO Equalization, CQI etc.
• Expert in mapping standards requirements to algorithm design and generating HW and SW design specifications for multi-core SoC.
• Fluent in fixed-point PHY simulations: Matlab, C/C++.
• Must have good understanding of WCDMA/HSPA+ PHY layer standards. Experience with R7 and R8 HSPA+ features is a strong plus.
• Experience with algorithm optimization for ASIC implementation or DSP is a plus.
• Experience in working closely with test teams for evaluating and debugging Modem in a lab and field environment is a plus.
• Must have the ability to multi-task in a fast-paced, dynamic environment; inherent sense of urgency and accountability.
• Must demonstrate good analysis and problem-solving skills and have effective interpersonal, teamwork, and communication skills. 
• Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision. 

• Represent Cavium to top five enterprise customers.
• Quality and Reliability advocate for top five customers within Cavium.
• Generate and communicate customer qualification plans.
• Drive Cavium and its suppliers to execute customer qualifications.
• Manage customer action requirements and drive to completion.
• Proactively review customer quality metrics and prevent quality accidents.
• Manage customer audits and close all action items.
• Mitigate customer complaints.
• Prepare effective analytical reports for distribution to customers.
• Represent design engineering with customers.
• Provide guidance to design engineering for DFQ, DFR, DFFA.

• BSET, BSEE, or BS degree in a related field plus 10 years of experience in QC/QA, Design, Field Applications or Product/Test Engineering experience.
• Able to lead cross-functional teams and manage complex projects.
• Be an agent of change; able to write specifications, change notices, and customer letters.
• 3 years program management recommended.
• Knowledge of Semiconductor Wafer Processing, including defect density effects on yield and fault coverage, and knowledge of Semiconductor Assembly, Test, and Finish.
• Experience in Semiconductor Design and/or NPI and experience with enterprise customers.
• Knowledge of on-line SPC and problem solving methodologies.
• Understanding of semiconductor operations and printed circuit board manufacturing processes.
• Inherent sense of urgency and accountability; self-starter able to influence/drive others.
• Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.   Ability to analyze problems and propose solutions.
• Effective interpersonal, teamwork, computer, and communication skills; able to interface internally and externally with all levels of the organization.
• Willingness to collaborate with global team members in various time zones.
• Willingness to travel frequently.   Ability to speak more than one language may be helpful.

• Solid GDB and debugging tools development experience.
• Knowledge of internals of GCC, BINUTILS and GLIBC.
• Knowledge of low-level debug tools (EJTAG, Protocol analyzers, etc).
• Knowledge of the MIPS CPU Architecture a huge plus.
• Excellent programmer in C and assembly.
• Experience with working on SMP systems with high CPU count.
• Must have effective interpersonal/teamwork/communication skills, and demonstrate good analysis and problem-solving skills.
• Self directed, with inherent sense of urgency and accountability; ability to multi-task in a dynamic, fast-paced environment.
• Minimum of a Bachelor’s Degree in Computer Science or in Electrical/Electronics Engineering; Master’s Degree is preferred.
• Minimum of 8 years of relevant work experience. 

Responsibilities:

• New-product qualification before volume production, as well as new package/fab qualification.
• Perform customer return analysis, and ensure adequate test coverage.
• Work with design and DFT/DFM groups to define and enhance yield and test methodology.

• BSEE or MSEE
• Minimum 2+ years of experience in semiconductor product engineering.
• Solid background in ATE testing (critical skill), test methodology, silicon process, DFT/DFM, and high-speed, digital-testing experience required.
• Agilent 93K, and Credence experience is preferred.
• Microprocessor and Network Processor experience is a strong plus.
• Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision. Inherent sense of urgency and accountability; able to multi-task in a dynamic, fast-paced environment.
• Excellent verbal and written communication skills.
• Effective interpersonal, teamwork, and communication skills; able to interface internally and externally with all levels of the organization.

• Troubleshoot, diagnose, and resolve complex customer incidents in a timely manner via our advanced Support CRM System; work on site with the customer as required.
• Maintain daily updates in the database on the progress with customer issues.
• Review and assist in the debugging of customer and partner OS, boot-loader, and application code.
• Installation, test, and benchmarking of Cavium reference software and software development kits; configuration and use of application software including IPSec/IKE, SSL, WLAN, 7-layer network stacks.
• Guidance and assistance in development of customer hardware, test software, device drivers, API's, and application software.
• Participate in conference calls with Customers and Sales/FAEs as necessary.
• Interface with other technical support personnel, engineering, and product management to escalate and resolve issues.
• Replicate issues and testing of customer configurations in a lab environment.
• Author technical knowledgebase articles (FAQs) for use by customers, other technical support personnel, and partners, based on closed issues.
• Develop training materials on your designated subject-matter area of expertise.
• Review and provide feedback on Cavium technical documents, specifications, manuals, app notes, white papers, product briefs, etc.

• Bachelor’s Degree in Computer Science or Computer/Electrical Engineering.
• 5+ years of work experience in the field of 32b and 64b microprocessors & integrated SoCs (Preferably MIPS, ARM, or PowerPC).
• Previous experience in either a technical support engineering or FAE role is desired.
• Knowledge or Experience in:
• Networking protocols, software, systems, and equipment.
• C programming, troubleshooting, performance analysis in embedded systems environment.
• OS internals, binutils and C libraries in Linux, UNIX, xBSD, VxWorks, or similar operating system (Preferably Android as well).
• GNU tool chain, gcc, gdb.
• Device Driver/API development.
• U-boot boot-loader porting.
• Common microprocessor architectures and assembly language programming.
• Writing app notes, technical papers, technical specifications.
• Familiarity with:
• Network security (IPSec/SSL) and/or Layer 2-7 applications.
• PCB / Board design and bring-up practices.
• Circuit design and schematic capture / layout principles.
• Debugging and measurement tools such as EJTAG debugger tools, oscilloscopes, logic analyzers, and other test equipment.
• High speed communications protocols and interfaces such as XAUI, SGMII, PCI-X, PCI-Express, Serial RapidIO, SPI4.2, Interlaken, DDR2/DDR3 SDRAM, etc.
• Datasheets and electrical / mechanical parameters.
• Willingness to collaborate with global team members in various time zones.
• Organized, Self-driven and Customer focused.
• Excellent oral and written English communication skills.
• Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.  Inherent sense of urgency and accountability; able to multi-task in a dynamic, fast-paced environment.
• Effective interpersonal, teamwork, and communication skills; able to interface internally and externally with all levels of the organization.
  

Responsibilities:

• Participate in architectural design decisions such as hardware/software tradeoffs; hands-on position.
• Participate in the testing process by coding test applications, module-level test review, system-level test review, analysis, and test implementation.
• Implement multi-module application/function based on specifications.
• Exercise judgment based on technical experience and rely on experience and technical judgment to plan and accomplish goals
• Exercise engineering judgment to achieve design/product goals with minimal
  supervision

• BS in Computer Science (CS) or Electrical Engineering (EE) with 7-11 years of experience, MS in CS/EE with 5-9 years of experience, PhD in CS/EE with 2-6 yrs experience.
• Knowledge of a variety of fields’ concepts, practices, and procedures within area of development with demonstrated proficiency in one area of expertise.
• Perform a variety of tasks with minimal supervision; able to own independent section of design.
• Capable of handling independent projects or multi-module sections of a complex design.
• Background in Networking, Embedded Systems, and both C/C++  and  Multi-Core Programming.
• Good at data-structure implementation.
• Good at algorithms, Complexity Analysis and Space/Time Tradeoffs.
• Algorithm Experience:  L2-L4 Packet Classification, Regular Expression, Concurrent Algorithms.
• Knowledge of OS concepts: multi-tasking, memory management, interrupts, drivers, etc.
• Knowledge of CPU architecture.
• Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.  Inherent sense of urgency and accountability; able to multi-task in a dynamic, fast-paced environment.
• Excellent verbal and written communication skills.
• Effective interpersonal, teamwork, and communication skills; able to interface internally and externally with all levels of the organization.   

Senior Software Engineer
Title: Senior Software Engineer
Location: San Jose, CA office
Department: CTO
Job Code: SERG05

Description:
DDesign, modify, develop, code, and implement modules based on specifications.

Responsibilities:

• Participate in architectural design decisions such as hardware/software tradeoffs;  hands-on position.
• Participate in the testing process by coding test applications, module-level test review, system-level test review, analysis, and test implementation.

• Bachelor’s  or Master’s degree in either Computer Science or Electrical Engineering.
• Minimum 4-5 years of experience.
• Background in Networking, Embedded Systems, and both C/C++  and  Multi-Core Programming.
• Good at data-structure implementation.
• Good at algorithms, Complexity Analysis and Space/Time Tradeoffs.
• Algorithm Experience:  L2-L4 Packet Classification, Regular Expression, Concurrent Algorithms.
• Knowledge of OS concepts: multi-tasking, memory management, interrupts, drivers, etc.
• Knowledge of CPU architecture.
• Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.  Inherent sense of urgency and accountability; able to multi-task in a dynamic, fast-paced environment.
• Excellent verbal and written communication skills.
• Effective interpersonal, teamwork, and communication skills; able to interface internally and externally with all levels of the organization.    

Sr. Software Engineer – OCTEON
Title: Sr. Software Engineer (OCTEON)
Location: San Jose, CA office
Department: Software Engineering
Job Code: SEFM09

Description:
Develop and support software for Cavium’s OCTEON line of products, contribute to performance and/or feature  enhancements of the existing software package (including various networking stacks), and work closely with customers to help them design and implement efficient software
for the OCTEON family of processors.

Requirements:

• Proven experience with solving real-time embedded issues, including: threading, optimization, memory management, interrupt handling, etc.
• Experience in troubleshooting, performance analysis, and performance optimization for embedded systems.
• 5+ years experience in embedded system programming.
• Excellent programming skills - C and assembly (preferably MIPS).
• Strong knowledge of networking protocol stacks (TCP/IP, UDP, IPsec, SSL, etc.).
• Knowledge of various debugging tools (EJTAG, probes, logic analyzers, etc.).
• Knowledge of OCTEON/MIPS CPU architecture and deep packet inspection/Snort.
• Linux kernel and device drivers (networking, PCI, etc.).
• Understanding of low level CPU architecture.
• Working experience with multi-core/multi-CPU environments.
• Effective interpersonal, teamwork, and verbal/written communication skills; able to interface internally and externally with all levels of the organization.
• Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision. Inherent sense of urgency and accountability; able to multi-task in a dynamic, fast-paced environment.
• Minimum: Bachelors Degree in Computer Science, Electrical Engineering or equivalent, M.S. preferred.

Sr. Product-Line Marketing Manager (Infrastructure Processor Group)
Title: Senior Product-Line Marketing Manager (Infrastructure Processor Group)
Location: San Jose, CA Office
Department: NCD Marketing
Job Code: PLSK09

Description:
Senior position in product-line marketing, managing multiple leading multicore SoC product families, specifically targeting next-generation mobile infrastructure and related networking applications.

Responsibilities:

• Develop detailed product-definition and market-penetration strategies.
• Drive lead-customer engagement and sales-design win efforts. 
• Develop overall product solution, including key Ecosystem partnerships. 
• Overall product lifecycle:  forecasting, product introduction, and pricing management.  
• Advocate Cavium-solution advantages to both press and analyst community via PR and relevant conference activities.
• Generate competitive assessments and marketing/sales strategies.

Requirements:

• Extensive experience in embedded-processor, product marketing/management with a high level of technical, customer, and application expertise in embedded mobile infrastructure applications for 3G/4G/LTE.
• Demonstrated experience and success in marketing and managing complex, programmable semiconductor products and driving design-wins with leading Tier1 OEM customers.
• Significant, detailed knowledge of the mobile infrastructure market, customers, and applications, combined with a strong understanding of current market trends and applications.
• Solid understanding of embedded-processor market, applications, and software development.
• Detailed knowledge and experience in DSP technologies is a significant plus.
• Experience in negotiating product requirements and working with large engineering teams to deliver compelling products in competitive markets within tight time-schedule requirements.
• Strong business sense and excellent time-management skills.
• Hands-on management:  focus simultaneously on big picture and driving implementation.
• Demonstrated analysis and problem-solving skills; diligent, detail-oriented, willing to take initiative and handle assignments with minimal supervision.  Inherent sense of urgency and accountability; ability to multi-task in a fast-paced, dynamic environment.
• Effective interpersonal, teamwork, and communication skills with the ability to interface externally with customers and internally with all levels of the organization.
• BS in Electrical/Computer/CS Engineering with 10+ years of related work experience (minimum 5 yrs. in business role)
• MS/MBA desired.

Sr. Test Engineer
Title: Sr. Test Engineer
Location: San Jose, CA office
Department: Operations
Job Code: TEED03

Responsibilities:
As a Senior Test Engineer you will be responsible for test program development on the Agilent 93K test platform. Other responsibilities include

• Design tester hardware for high speed testing.
• Develop characterization, production, and wafer sort test programs.
• Create all the documentation for detail test plans and test methodologies to meet product specifications.
• Involved in the testability review (DFT & DFM) of complex processor devices.
• Test pattern conversion from design simulation environment to ATE format.
• Test time reduction, yield improvement, and release of production test programs with product engineers.
  

Requirements:

• BS or MS (Preferred)
• Minimum 6+ yrs of test program development experience on the Agilent 93K ATE test platform. Strong knowledge of C/C++, Perl, and Unix environment.
  

• Work with the Architecture team, and as a design-team member, shape the micro-architecture of the chip, and write specifications for the relevant block, micro-architecture of the block, design implementation using RTL coding techniques, Synthesis, place and route, and timing signoff.
• Work with the Verification team on pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis, and full-chip simulation plus debug. 
• Work with the physical design teams in aiding the implementation of the functional blocks.

• BS/MS/PhD in EE or equivalent required with up to 5 years of experience in RTL design of submicron SOC products (eg:  Microprocessor based SOC’s).
• Experience in Micro-architecture for the complex Custom/ASIC products focusing in any one/more areas:  NPU, Embedded Processors, DSP, Graphics, and/or general purpose microprocessors. 
• RTL design experience, Synthesis, static-timing closure, formal verification, gate-level simulations and block-level function verification.
• Design knowledge of one/more industry-standard bus interfaces (PCIe, SPI, SRIO, USB, XAUI, etc.) and memory interfaces (DDR2, DDR3, etc.) are a plus.
• Hands-on experience for all aspects of chip-development process with proficiency in front-end design tools and methodologies is a plus.
• Experience in designing high speed (>1 GHz)/high-performance embedded processor SOC products is a plus.
• Knowledge of scripting languages such as Perl, Tcl, and UNIX shell, etc. is desirable.
• Must possess good communication skills.
• Self driven individual and a good team player.
• Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.  Inherent sense of urgency and accountability; able to multi-task in a dynamic, fast-paced environment.
• Excellent verbal and written communication skills.
• Effective interpersonal, teamwork, and communication skills; able to interface internally and externally with all levels of the organization.

• Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers. 
• Write a verification test plan using random techniques and coverage analysis, and work with designers to ensure it is complete. 
• Build a constrained random environment for design blocks or full-chip testing. 
• Develop tests and tune the environment to achieve coverage goals. 
• Debug failures and work with designers to resolve issues. 
• Turn verification tests into hardware-test patterns. 

• BSCS/EE or equivalent required, with 2 -10 years of functional design-verification experience.
• Good programming skills using C++ and verilog.
• Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment.
• Experience with scripting language such as Perl and EDA Verification tools.
• Good understanding of Linux O.S. and networking protocols a plus.
• Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision. 
• Effective interpersonal, teamwork, and communication skills; able to interface internally and externally with all levels of the organization.   

• Good understanding of software/firmware/hardware partitioning and interaction in complex systems on a chip (SoC).
• Strong knowledge of common system hardware interfaces (PCI-Express, DDR3 memory, I2C, etc.), communication interfaces (XAUII, SGMII, RGMII, etc.), and the GCC-based tool set.
• Demonstrated ability to troubleshoot complex systems and resolve failures in both software and hardware.
• Familiarity with Linux, device drivers, and/or writing embedded software applications.
• Experience with networking test equipment, logic analyzers, and oscilloscopes.
• Good understanding of networking protocols and stacks.
• Knowledge of Serial Rapid-IO, PCI Express, and/or Interlaken.  
• Self directed, with inherent sense of urgency and accountability; ability to multi-task in a fast-paced environment.
• Excellent verbal and written communication skills.
• BSEE, BSCS or equivalent with 5+ years experience working with low-level machine facilities from a high-level language (C or similar).

• Design custom VLSI digital circuits for high-speed processor chips in leading-edge CMOS process technology targeted at network and consumer applications.
• Design circuits from behavioral description.
• Develop schematics, perform circuit/timing analysis, oversee layout design work, and perform various CMOS backend-design quality checks.

• BSEE or equivalent required with 2-5 years of experience in full custom digital circuit design.
• Experience with industry standard EDA tools (HSPICE, Virtuoso, Prime Time) is a plus.
• Good understanding of hardware description language (such as verilog) and scripting language (such as Perl) is a plus.
• Good verbal and written communication skills.
• Self-driven individual and a good team player.

Responsibilities:

• In-house expert on scan, BIST, functional patterns, jtag, and SERDES testing.
• Ability to work with a wide breadth of testing scenarios which are sometimes beyond the scope of what commercially-available tools can support.  (In addition to standard cells, Cavium products have full, custom, digital logic, analog IO/SERDES, rams, and cams.)
  

Requirements:

• Experience with Verilog, scan and functional patterns a must.
• Demonstrated expertise in structural test, BIST, functional test, and other test/coverage methodologies.
• Experience and knowledge of: 
  • RTL design using Verilog;
  • Functional verification, especially of DFt features;
  • Test-pattern generation (both functional and structural);
  • high-volume test equipment (ATE) and methods (e.g, system functional testing).
• Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.  Inherent sense of urgency and accountability; able to multi-task in a dynamic, fast-paced environment.
• Effective leadership, influencing, interpersonal, teamwork, and communication skills; able to interface internally and externally with all levels of the organization.
• BSEE or equivalent with 10+ years of experience in design for test. 
  

• Masters and PhD level recent graduate or experienced candidate with equivalent experience required.
• Self-motivated individual with good understanding of mixed signal design, signal processing, and noise analysis will have the opportunity to be exposed to a broad variety of projects at both the architectural and circuit levels, as well as to participate in the development of an expanding mixed signal design group.

Mixed Signal Mask Designer
Title: Mixed Signal Mask Designer
Department: Hardware Engineering
Location: Marlborough, MA
Job Code: MSSM01

The position involves design of mixed signal layout masks for use in leading edge network microprocessors implemented in the most advanced CMOS process technologies.

Potential areas of layout design tasks include:

• PLLs and DLLs for clock generation and distribution
  
• Clock and data recovery (CDR) design for multiple SERDES standards
• Wireline transmitters, receivers, and equalizers
• Voltage regulation and reference generation

The candidate should have working knowledge of the Cadence design environment (Virtuoso), as well as experience running DRC, and LVS. In addition, experience with and understanding of analog specific layout techniques and methodologies are required. Scripting ability in Skill and/or PERL is a plus, as is a basic understanding of circuits. A minimum of 5 years of layout experience is required.

Analog CAD Engineer
Title: Analog CAD Engineer
Department: Hardware Engineering
Location: Marlborough, MA
Job Code: ACSM01

The position is for a lead role in CAD support of the analog design team at Cavium’s Marlboro, MA design center.

Requirements:

• Cadence skill scripting
• Familiarity with PDK setup and associated tool runsets
• Schematic netlist post processing and parasitic back-annotation
• Post-processing of layout parasitic extraction
• PERL , C/C++ scripting required
• TCL, MATlab scripting a plus
• Basic understanding of circuit elements and parasitics as associated with a netlist
• Analog layout skills a plus