Job Descriptions:
 Jobs in San Jose, CA
Jobs in Marlborough, MA office and other east coast locations
Wireless System Specialist – Modem IOT
Title: Wireless System Specialist – Modem IOT
Location: San Jose, CA office
Department: Wireless Broadband Group
Job Code: WSJF09
Description:
This position is part of the Design Team which is responsible for the design, execution, and automation of system tests to ensure the quality of Cavium's next-generation Modem systems.
Responsibilities:
- Ensure that the products meet the specification and performance metrics for WCDMA/HSPA+ and LTE base-station modems.
- Work with Modem System, DSP, and Protocol SW groups to identify quality risks in time to ensure that both project-quality goals and schedules are met.
- Develop automated scripts and test infrastructure to validate the Modem.
- Operate and set up the Modem IOT lab, while guiding junior members in the System Test Team to calibrate and use test equipment, such as Protocol Tester, Radio Channel Emulator, Signal Generators, and Power Meters.
- Work closely with developers in order to reproduce, analyze, and debug internal defects during system testing; in addition, address customer issues found in the field.
- Partner with the Teams and help drive defect-prevention initiatives.
Requirements:
- At least 3+ years of prior experience in LTE, WCDMA/HSPA+ standards with focus on Modem Protocol Tests.
- Strong expertise in software debugging tools used in Real-Time development.
- Expert in mapping standards requirements to System-Test specifications.
- Expert in at least one of LTE or WCDMA/HSPA+ E2E system architectures -- including a good understanding of X2/S1/O&M interfaces.
- Expert in C/C++ and scripting language such as shell/python.
- Must have expertise in higher-layer protocol stack (MAC/RLC/RRC/PDCP/NAS/USIM).
- Must be hands-on with lab set-up and equipment such as Spectrum Analyzers, Protocol Testers, Signal Generators, and Vector-Signal Analyzers; must be familiar with 3rd party test SW tools such as Wire-Shark, ASN Decoder.
- Expertise in developing and debugging TTCN tests.
- Multi-disciplinary knowledge in two or more Wireless Communication Systems with good understanding of Mobile Radio propagation.
- Experience with GCF and PTCRB certification process is a strong plus.
- Prior experience in developing and testing protocol stack features for 3G or LTE is a strong plus.
- Experience using Linux environment (rpm, bash, sh, ssh, ftp, route, etc.).
- Prior experience in intrusive testing on embedded platform running an RTOS.
- Working knowledge of internet protocols, such as TCP/IP, SIP and QoS management.
- Must be diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision. Inherent sense of urgency and accountability; able to multi-task in a dynamic, fast-paced environment.
- Effective interpersonal, teamwork, and communication skills; demonstrate good analysis and problem-solving skills, communicate defects concisely, and accurately prioritize them. Able to interface internally and externally with all levels of the organization.
- BS in Electrical or Computer Engineering with a minimum of 5 years of related experience, or MS in Electrical or Computer Engineering with a minimum of 3 years of related experience.
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Sr. Linux Kernel Engineer
Title: Sr. Linux Kernel Engineer
Location: San Jose, CA office
Department: Software NCD Group
Job Code: LKPK09
Description:
Function as part of the Cavium Networks platform software team and implement low-level software for 32 CPU Octeon SoCs.
Requirements:
- Solid low-level OS kernel and chip-programming experience and experience with writing device drivers (PCI, USB, Ethernet etc).
- Skilled in programming software workarounds for chip errata in a timely fashion.
- Knowledge of networking protocol stacks and their requirements for hardware-packet IO engines.
- Co-ordinate with hardware team to isolate issues and suggest best possible solutions from software point of view.
- Knowledge of low level debug tools (EJTAG, Protocol analyzers, etc).
- Excellent programmer in C and assembly
- Knowledge of hardware packet IO engines (network processors etc) and low-level PCIe experience a huge plus.
- Experience with working on SMP systems with high CPU count.
- Must have effective interpersonal/teamwork/communication skills, demonstrate good analysis and problem-solving skills, and be able to multi-task in a fast paced environment.
- Self directed, with inherent sense of urgency and accountability; ability to multi-task in a dynamic, fast-paced environment.
- Minimum of a Bachelor’s Degree in Computer Science or in Electrical/Electronics Engineering; Master’s Degree is preferred.
- Minimum of 8 years of relevant work experience.
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Sr. Architect
Title: Sr. Architect
Location: San Jose, CA office
Department: Software NCD Group
Job Code: SAPK09
Description:
Lead, hands-on position to help tier-1 customers with architecting and optimizing critical software solutions.
Responsibilities:
- Work internally on Cavium’s software products to identify the most customer-visible bottlenecks and implement solutions.
- Contribute towards new feature/product development.
Requirements:
- In-depth knowledge of Linux kernel, bare-metal programming environments and low-level CPU architecture.
- Excellent communications skills with the ability to engage with important customers to help architect and optimize software solutions.
- Skills associated with profiling and optimization of control-plane and data-plane software.
- Excellent programmer in C, with a working knowledge of assembly programming.
- Experience with packet processing hardware.
- Deep familiarity with writing low-level system software for embedded systems.
- Familiarity with multi-core SMP programming environments.
- Additional skills which are a plus: familiarity with the Octeon CPU; expertise in networking protocol stacks (IP/TCP/IPSec/SSL etc); expert in MIPS architecture and assembly programming; and experience working with European and Asian Telecom/Networking companies.
- Must have effective interpersonal/teamwork/communication skills, demonstrate good analysis and problem-solving skills, and be able to multi-task in a fast paced environment.
- Self directed, with inherent sense of urgency and accountability; ability to multi-task in a dynamic, fast-paced environment.
- Minimum of a Bachelor’s Degree in Computer Science/Electrical/Electronics Engineering.
- Minimum of 8 years of relevant experience.
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Sr. Product-Line Marketing Manager (Infrastructure Processor Group)
Title: Senior Product-Line Marketing Manager (Infrastructure Processor Group)
Location: San Jose, CA Office
Department: NCD Marketing
Job Code: PLSK09
Description:
Senior position in product-line marketing, managing multiple leading multicore SoC product families, specifically targeting next-generation mobile infrastructure and related networking applications.
Responsibilities:
- Develop detailed product-definition and market-penetration strategies.
- Drive lead-customer engagement and sales-design win efforts.
- Develop overall product solution, including key Ecosystem partnerships.
- Overall product lifecycle: forecasting, product introduction, and pricing management.
- Advocate Cavium-solution advantages to both press and analyst community via PR and relevant conference activities.
- Generate competitive assessments and marketing/sales strategies.
Requirements:
- Extensive experience in embedded-processor, product marketing/management with a high level of technical, customer, and application expertise in embedded mobile infrastructure applications for 3G/4G/LTE.
- Demonstrated experience and success in marketing and managing complex, programmable semiconductor products and driving design-wins with leading Tier1 OEM customers.
- Significant, detailed knowledge of the mobile infrastructure market, customers, and applications, combined with a strong understanding of current market trends and applications.
- Solid understanding of embedded-processor market, applications, and software development.
- Detailed knowledge and experience in DSP technologies is a significant plus.
- Experience in negotiating product requirements and working with large engineering teams to deliver compelling products in competitive markets within tight time-schedule requirements.
- Strong business sense and excellent time-management skills.
- Hands-on management: focus simultaneously on big picture and driving implementation.
- Demonstrated analysis and problem-solving skills; diligent, detail-oriented, willing to take initiative and handle assignments with minimal supervision. Inherent sense of urgency and accountability; ability to multi-task in a fast-paced, dynamic environment.
- Effective interpersonal, teamwork, and communication skills with the ability to interface externally with customers and internally with all levels of the organization.
- BS in Electrical/Computer/CS Engineering with 10+ years of related work experience (minimum 5 yrs. in business role)
- MS/MBA desired.
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Customer
Quality Engineer
Title: Customer Quality Engineer
Location: San Jose, CA office
Department: Quality and Reliability
Job Code: CQMB09
Description:
Manage top five customer quality and reliability programs,
represent Cavium to top five customers, and be the quality
and reliability advocate for top five customers within Cavium.
Responsibilities:
Primary Responsibility: Improve customer satisfaction
of Cavium’s top five customers:
- Generate and communicate customer qualification plans
- Drive Cavium and its suppliers to execute customer qualifications
- Manage customer action requirements and drive to completion
- Proactively review customer quality metrics and prevent
quality accidents
- Manage customer audits and close all action items.
- Mitigate customer complaints
- Prepare effective analytical reports for distribution
to customers
Requirements:
- 3+ years of Program Management recommended
- ISO 9000 Lead Assessor training
- Knowledge of Semiconductor Wafer Processing, Semiconductor
Assembly, and Semiconductor Test and Finish
- Understand semiconductor operations and printed circuit
board manufacturing processes.
- Knowledge of on-line SPC and problem solving methodologies
- Lead cross functional teams and manage complex projects,
work with minimal supervision, self-start and influence/drive
others, and be an agent of change.
- Ability to analyze problems and propose solutions, and
write specifications, change notices and customer letters
- Demonstrate good analysis and problem-solving skills;
diligent, detail-oriented, willing to take initiative and
handle assignments with minimal supervision. Inherent sense
of urgency and accountability; ability to multi-task in
a fast-paced environment.
- Effective interpersonal, teamwork, and communication skills.
- Ability to travel frequently; ability to speak foreign
languages helpful
- BSET, BSEE, or BS degree in a related field.
- 10+ years of QC/QA experience in the Semiconductor Industry
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Sr. Test Engineer
Title: Sr. Test Engineer
Location: San Jose, CA office
Department: Operations
Job Code: TEED03
Responsibilities:
As a Senior Test Engineer you will be responsible
for test program development on the Agilent 93K test platform.
Other responsibilities include
- Design tester hardware for high speed testing.
- Develop characterization, production, and wafer sort
test programs.
- Create all the documentation for detail test plans and
test methodologies to meet product specifications.
- Involved in the testability review (DFT & DFM) of
complex processor devices.
- Test pattern conversion from design simulation environment
to ATE format.
- Test time reduction, yield improvement, and release of
production test programs with product engineers.
Requirements:
- BS or MS (Preferred)
- Minimum 6+ yrs of test program development experience
on the Agilent 93K ATE test platform. Strong knowledge of
C/C++, Perl, and Unix environment.
Senior Office Assistant
Title: Senior Office Assistant
Department: NCD IC Engineering
Location: Marlborough , MA
Job Code: OABF09
Description:
General office support for all managers and employees. Maintain local records. Receive/review all incoming correspondence and handle routine/recurring inquiries; direct the rest appropriately.
Responsibilities:
- Maintain publications, log books, in-house program documentation and other forms of documentation, and ensure that they are accurate, current, and complete.
- Create/maintain purchase orders for recurring, general/direct-bill purchases, track/update purchase orders, collect appropriate receipts and bills of lading, and forward as appropriate to corporate headquarters.
- Inventory and stock all supplies (office, kitchen, snacks, coffee, soda).
- Support the Recruitment process for Managers by scheduling interviews, confirming travel arrangements, providing/verifying expense reports, and handling start-up tasks (business cards, nameplates, etc.).
- Forwards timecards to the corporate office for payroll processing.
- Plan and execute all outings, events, and activities for the Marlborough, MA location.
- Participate as needed in special division/departmental projects.
- Supervise the maintenance of standard office equipment, and distribute building-access keys.
- Assist Teams/Managers with external client or customer meetings.
- Point-person with office-park Management Company regarding any office-building issues.
- Participate in planning and execution of office expansion and moves as needed.
Requirements:
- Professional appearance and manner, good planning and organizational skills.
- Diligent, detail-oriented, willing to take initiative and handle assignments with minimal supervision. Inherent sense of urgency and accountability; able to multi-task in a dynamic, fast-paced environment.
- Excellent verbal and written communication skills; well versed in using Microsoft Office.
- Effective interpersonal, teamwork, and communication skills; able to interface internally and externally with all levels of the organization.
- Able to maintain confidentiality and demonstrate discretion in the workplace.
- High-school diploma or GED required; College Degree preferred.
- Minimum of 2-5 years of experience in an office environment.
Verification Engineer
Title: Verification Engineer
Department: Hardware Engineering
Location: Marlborough, MA office
Job Code: VEJE02
Requirements:
- BSCS/EE or equivalent required with 2 to 10 years of functional design verification experience.
- Good programming skills using C++ and verilog.
- Experience with writing a detailed test plan and building a sophisticated directed random verification environment.
- Experience with scripting language such as Perl and EDA Verification tools.
- Good understanding of Linux O.S. and networking protocols a plus.
- Team player is a must.
Description:
Contributes as a verification engineer as part of a world class leading edge processor design team. This includes developing the architecture for a functional verification environment including reference models and bus functional monitors and drivers. Writing a verification test plan using random techniques and coverage analysis and working with designers to make sure it is complete. Building a constrained random environment for design blocks or full chip testing. Developing tests and tuning the environment to achieve coverage goals. Debugging failures and working with designers to resolve issues. Turning verification tests into hardware test patterns.
RTL Design Engineer
Title: RTL Design Engineer
Department: Hardware Engineering
Location: Marlborough, MA office
Job Code: DEPA03
Requirements:
- BS/MS/PhD in EE or equivalent required with up to 5 years of experience in RTL design of submicron SOC products (e,g; Microprocessor based SOC’s).
- Experience in Micro-architecture for the complex Custom/ASIC products focusing in any one/more areas: NPU, Embedded Processors, DSP, Graphics and/or general purpose microprocessors.
- RTL design experience, Synthesis, static timing closure, formal verification, gate level simulations & block level function verification.
- Design knowledge of one/more industry standard bus interfaces ( PCIe , SPI, SRIO, USB, XAUI etc; ) and memory interfaces (DDR2, DDR3 etc;) is a plus.
- Experience in interfacing with architecture and Physical implementation teams is a plus.
- Hands on experience for all aspects of chip development process with proficiency in front end design tools and methodologies is a plus.
- Experience in designing high speed (>1 GHz) /high performance embedded processor SOC products is a plus.
- Knowledge of scripting languages such as Perl, Tcl and UNIX shell etc is desirable
- Must possess good communication skills.
- Self driven individual and a good team player.
Description:
This is an entry to mid level RTL design position. You area expected to contribute to the development of one or more Coprocessor units, industry standard high speed serial bus interfaces for Cavium’s next generation Multi-core embedded MIPS64 processor family targeted at Networking, Storage, Security & Wireless applications in the state of the art deep sub-micron CMOS process technologies. Work with the architecture team and as a design team member, shape the micro-architecture of the chip, and write specifications for the relevant block, micro-architecture of the block, design implementation using RTL coding techniques, Synthesis, place & route and timing sign off.
Individual also works with the verification team on pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis and full chip simulation plus debug. Also, work with the physical design teams in aiding the implementation of the functional blocks.
Mixed Signal Circuit Design Engineer
Title: Mixed Signal Circuit Design Engineer
Department: Hardware Engineering
Location: Marlborough, MA
Job Code: MCSM04
Requirements:
- Masters and PhD level recent graduate or experienced candidate with equivalent experience required.
- Self-motivated individual with good understanding of mixed signal design, signal processing, and noise analysis will have the opportunity to be exposed to a broad variety of projects at both the architectural and circuit levels, as well as to participate in the development of an expanding mixed signal design group.
Description:
The position involves design of mixed signal circuits/systems for use in leading edge network microprocessors implemented in the most advanced CMOS process technologies. Some potential areas of design tasks include PLLs, DLLs, CDRs, SERDES, voltage regulation and reference generation, and memory interfaces. A successful candidate will demonstrate a strong understanding of mixed signal fundamentals.
Mixed Signal Mask Designer
Title: Mixed Signal Mask Designer
Department: Hardware Engineering
Location: Marlborough, MA
Job Code: MSSM01
The position involves design of mixed signal layout masks for use in leading edge network microprocessors implemented in the most advanced CMOS process technologies.
Potential areas of layout design tasks include:
- PLLs and DLLs for clock generation and distribution
- Clock and data recovery (CDR) design for multiple SERDES standards
- Wireline transmitters, receivers, and equalizers
- Voltage regulation and reference generation
The candidate should have working knowledge of the Cadence design environment (Virtuoso), as well as experience running DRC, and LVS. In addition, experience with and understanding of analog specific layout techniques and methodologies are required. Scripting ability in Skill and/or PERL is a plus, as is a basic understanding of circuits. A minimum of 5 years of layout experience is required.
Analog
CAD Engineer
Title: Analog CAD Engineer
Department: Hardware Engineering
Location: Marlborough, MA
Job Code: ACSM01
The position is for a lead role in CAD support of the analog
design team at Cavium’s Marlboro, MA design center.
Requirements:
- Cadence skill scripting
- Familiarity with PDK setup and associated tool runsets
- Schematic netlist post processing and parasitic back-annotation
- Post-processing of layout parasitic extraction
- PERL , C/C++ scripting required
- TCL, MATlab scripting a plus
- Basic understanding of circuit elements and parasitics
as associated with a netlist
- Analog layout skills a plus
The successful candidate will have the opportunity to become
part of a growing design team that is working on a wide variety
of high speed mixed signal design problems.
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